Showing posts with label Power Transistor. Show all posts
Showing posts with label Power Transistor. Show all posts

Thursday, October 27, 2011

Eppes, Milanovic, and Quarshie Present Paper at COMSOL Conference

Surface temperatures (C) in a transistor/heat sink assembly

Tom Eppes, associate professor of electrical and computer engineering, CETA; Ivana Milanovic, associate professor of mechanical engineering, CETA; and George Quarshie, electrical engineering student, presented a research paper at the annual COMSOL Users conference, which took place earlier this month in Newton, Mass. COMSOL performs finite-element modeling for various physics and engineering applications, in particular those that involve coupled interdisciplinary phenomena.

The paper, "Power Transistor Heat Sink Design Trade-offs,” discusses the heat transfer process in a TO-220 transistor package and the benefits of certain design features. Power transistors require heat sinks to dissipate thermal energy and keep junction temperatures below the recommended limit. A significant increase in useful life can be achieved by a small reduction in operating temperature. Parametric studies of heat sink size, emissivity and convective cooling coefficient estimate their impact on the steady-state temperature of the assembly. This work was initiated and done in part during the new course ES 591 Multiphysics Modeling.